5th Workshop on VHDL for Digital Systems, 28-30 April 2008

This workshop is designed to offer an in-depth coverage of digital hardware design with VHDL. The participants will be first introduced to the various choices available for implementing application specific digital systems such as FPGAs and ASICs. Subsequently, the FPGA design flow, which exemplifies the typical computer aided design (CAD) flow for developing digital hardware is presented. In addition to providing a comprehensive introduction to VHDL language concepts, the course will also offer a strong foundation in advanced VHDL RTL coding styles and methodologies for synthesizing efficient hardware. This is followed by a detailed study of the various methodologies for verifying digital designs including strategies for testbench generation and hardware modeling.

The lectures, which include numerous practical examples, will be complemented by lab sessions comprising of hands-on design exercises using state-of-the-art FPGA design tools. The labs will provide the participants with a detailed understanding of the salient features of the design tools as well as the opportunity to implement and test the VHDL designs on different devices from leading FPGA manufacturers. <back>