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Welcome to the CHiPES Digital Library. Research at CHiPES has lead to numerous research papers and whitepapers.
Refereed Conferences:
2007
R. K. Satzoda, Huy Nguyen Quang, C.H.Chang, "Programmable Montgomery Modular Multiplier for Trinomial Reduction Polynomials in GF(2^m)," International Symposium on Integrated Circuits, Singapore, September 2007. |
Dipnarayan Guha, T.Srikanthan, "Select asynchronous design styles in application-driven operating system-less embedded processors," International Symposium on Integrated Circuits, Devices and Systems (ISIC), Singapore, September 2007. |
Dipnarayan Guha, Duong Hoang Linh, Muhamed Fauzi Bin Abbas, T.Srikanthan, "PHY/MAC firmware enhancements to enable content processing in IEEE 802.15.3a-based embedded platforms," IEEE International Conference on Ultra Wide Band (ICUWB), Singapore, September 2007. |
S.Suchitra, R.K.Satzoda, T.Srikanthan, "Unified CORDIC based processor for Image Processing," International Conference on Digital Signal Processing, pp.343-346, UK, July 2007. |
Ashish Panda, Neha Tripathi, T.Srikanthan, "Improved Spectral Subtraction Technique for Text-Independent Speaker Verification," International Conference on Digital Signal Processing, pp.595-598, UK, July 2007. |
S. Suchitra, T.Srikanthan, C.T.Clarke, "Real Time Tracking of Camera Motion through Cylindrical Passages," International Conference on Digital Signal Processing, pp.455-458, UK, July 2007. |
X.F. Liao, J.G. Wu, T.Srikanthan, "Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Canada, July 2007. |
S.K. Lam, T.Srikanthan, "Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.89-94, Canada, July 2007. |
J.G.Wu, T.Srikanthan, G.Chen, "One-dimensional Search Algorithms for Hardware/Software Partitioning," Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007), France, May 2007. |
R. Mahesh, A.P.Vinod, "Frequency Response Masking based Reconfigurable Channel Filters for Software Radio Receivers," IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 2007. |
R. Mahesh, A.P.Vinod, "An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio Receivers," IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 2007. |
Smitha.K.G, A.P.Vinod, "A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters," IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 2007. |
A.Cui, C.H.Chang, "Watermarking for IP protection through template substitution at logic synthesis level," International Symposium on Circuits and Systems (ISCAS), USA, May 2007. |
Dipnarayan Guha, T.Srikanthan,"Compiler design techniques for efficiently translating radio protocol description machine language to hybrid asynchronous IS," IEEE International Symposium on Low-power and High-speed Chips (Cool Chips), Japan, April 2007. |
Dipnarayan Guha, T.Srikanthan, "Reconfigurable Frame Parser Design for multi-radio support on asynchronous microprocessor cores," IEEE Computer Society International Conference on Computing: Theory and Applications (ICCTA), Vol.1, pp. 122-127, India, March 2007. |
Yan Lin Aung, Douglas L. Maskell, "Operating System Support for Hardware Objects in a Reconfigurable Computing System," Proceedings of the Undergraduate Research Experience on CAmpus (URECA) @ NTU, pp. 54-56, February 2007. |
A.P. Vinod, A. Singla, C.H. Chang, "Low power differential coefficients-based FIR filters using hardware optimized multipliers" IET Proceedings on Circuits, Devices and Systems, February 2007.
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Dipnarayan Guha, T.Srikanthan, "Multi-radio realization on asynchronous processor cores," IEEE Consumer Communications and Networking Conference (CCNC), USA, January 2007. |
Duong Hoang Linh, Dipnarayan Guha, T.Srikanthan, "MB-OFDM UWB PHY layer detecting content," IEEE Consumer Communications and Networking Conference (CCNC), USA, January 2007. |
2006
| Xiaoyong Chen, Douglas L. Maskell, "Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 06), Singapore,December 2006. |
X. Chen, D.L. Maskell and Y. Sun, “Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’06), Singapore, December 2006. |
| Y. Wang, D.L. Maskell, J. Leiwo and T. Srikanthan, “Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’06), Singapore, December 2006. |
A.P.Vinod, Ankita Singla, Chip-Hong Chang and P.K.Meher, "Low power FIR filter realization using minimal difference coefficients: Part I – Complexity Analysis," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’06), Singapore, December 2006. |
A.P.Vinod, Ankita Singla, Chip-Hong Chang and P.K.Meher, "Low power FIR filter realization using minimal difference coefficients: Part II – Algorithm," 2006 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS ’06, Singapore, December 2006. |
Himanshu Thapliyal and A.P.Vinod, "CMOS realization of reversible TSG gate and reversible adder architectures," 2006 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS ’06, Singapore, December 2006. |
Smitha K.G., Hossam A.H.Fahmy and A.P.Vinod "Redundant adders consume less energy," 2006 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS ’06, Singapore, December 2006. |
J.Mathew, K. Maharatna, D.K.Pradhan and A.P.Vinod, "Exploration of power optimal implementation technique of 128-Pt FFT/IFFT for WPAN using pseudo-parallel datapath structure, " Tenth IEEE International Conference on Communication Systems, ICCS ’06, Singapore, November 2006. |
Zhao Chang, A.P.Vinod and P.K.Meher, "Reconfigurable architectures for low complexity software radio channelizers using hybrid filter banks," Tenth IEEE International Conference on Communication Systems, ICCS ’06, Singapore, November 2006. |
Dipnarayan Guha, Dipnarayan Guha, T.Srikanthan, "Ultra-wide band based sentient computing," 2006 International Symposium on Ubiquitous Computing Systems (UCS '06), Lecture Notes in Computer Science (LNCS), Seoul, Republic of Korea, October 2006. |
X. Chen, D.L. Maskell and Y. Sun, “Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions”, APCCAS’06, Singapore, 2006. |
R.Mahesh and A.P.Vinod, "Reconfigurable low complexity FIR filters for software radio receivers," Proceedings of the 17th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Helsinki, Finland, September 2006. |
A.P.Vinod, E. M-K. Lai and S. Emmanuel, "Implementation of low power and high-speed higher order channel filters for software radio receivers," Proceedings of the 17th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Helsinki, Finland, September 2006. |
Timothy Oliver and Douglas Maskell, “Execution Objects for Dynamically Reconfigurable FPGA Systems”, FPL’06, Madrid, Spain, Aug., 2006. |
Tham, K.S. and Maskell, D.L., “Software-oriented approach to Hardware-Software Co-simulation for FPGA-based RISC extensible processor”, FPL’06, Madrid, Spain, Aug., 2006. |
T.F. Oliver, B. Schmidt, J. Yanto and D.L. Maskell, “Accelerating the Viterbi Algorithm for Profile Hidden Markov Models using Reconfigurable Hardware”, Lecture Notes in Computer Science, Springer-Verlag, Vol. 3991, pp. 522-529, 2006. |
X. Chen and D.L. Maskell, “M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors”, Lecture Notes in Computer Science, Springer-Verlag, Vol 3894, pp. 191-201, 2006. |
Douglas L. Maskell, Jussipekka Leiwo and Jagdish C. Patra, “The Design of Multiplierless FIR Filters with a Minimum Adder Step and Reduced Hardware Complexity”, ISCAS 2006, Kos, Greece, 2006. |
Yu Yu, Jussipekka Leiwo & Benjamin Premkumar, "Hiding Circuit Topology from Unbounded Reverse Engineers," 11th Australasian Conference on Information Security and Privacy (ACISP'06), pp. 171-182, Australia, July 2006. |
R.K.Satzoda, S.Suchitra, T.Srikanthan,"Low Area-time Complexity Averaging Scheme for Thumbnail Generation," 3rd International Conference on Computer Graphics, Imaging and Visualization, Sydney, Australia, July 2006. |
R.K.Satzoda. C.H.Chang, T.Srikanthan, "Monte Carlo Statistical Analysis for Dynamic Power Simulation of RTL Designs using Synopsys Power Compiler," Synopsys Users Groups Conference, (on-line proceedings) Singapore, June 2006. |
L.P.Yan, T.Srikanthan, Nui Gang, "Area and Delay Estimation for FPGA Implementation of Coarse-Grained Reconfigurable Architectures," ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June 2006. |
K.G.Smitha, A.P.Vinod, "A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters," 2007 IEEE International Symposium on Circuits and Systems(ISCAS-2007), USA, May 2006. |
Y.He, C.H.Chang, "A Low-power, High-speed RB-to-NB Converter for
Fast Redundant Binary Multiplier," International Symposium on Circuits and Systems (ISCAS 2006), pp.2405-2408, Greece, May 2006. |
R. Mahesh and A. P. Vinod, “A New Common Subexpression Elimination Algorithm For Implementing Low Complexity FIR Filters in Software Defined Radio Receivers,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 4, pp. 4515-4518, Island of Kos, Greece, May 2006. |
A. P. Vinod, Ankita Singla and Chip-Hong Chang, “Improved Differential Coefficients-Based Low Power FIR Filters: Part I - Fundamentals,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 617-620, Island of Kos, Greece, May 2006. |
Yu Shao, C.H.Chang, "A Novel Hybrid Neuro-Wavelet System for Robust Speech Recognition," International Symposium on Circuits and Systems (ISCAS 2006), pp.1852-1855, Greece, May 06. |
Yu Shao, C.H.Chang, "A Kalman Filter based on Wavelet Filter-bank and Psychoacoustic Modeling for Speech Enhancement," International Symposium on Circuits and Systems (ISCAS 2006), pp.121-124, Greece, May 06. |
Yu Shao, C.H.Chang, "A Generalized Perceptual Time-Frequency Subtraction Method for Speech Enhancement," International Symposium on Circuits and Systems (ISCAS 2006), pp.21-24, Greece, May 06. |
R.K.Satzoda, S.Suchitra, T.Srikanthan, "Low Area-time Complexity Averaging Scheme for Thumbnail Generation," International Conference on Graphics, Images and Vision, Sydney and International Conference on Automation, Robotics and Vision, Singapore, April 2006. |
R.K.Satzoda, C.H.Chang, C.C.Jong, "High Speed Systolic Montgomery Modular Multipliers for RSA Cryptosystems," 5th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems (IMCAS '06), pp.240-245, China, April 2006. |
Y.Wang, Jussipekka Leiwo, T.Srikanthan, Yu Yu, "FPGA based DPA-resistant Unified Architecture for Signcryption," Third International Conference on Information Technology : New Generations, USA, April 2006. |
Yu Yu, Jussipekka Leiwo & Benjamin Premkumar, "A Study on the Security of Privacy Homomorphism", Third International Conference on Information Technology: New Generations (ITNG'06), pp. 470-475, USA, Apr 2006. |
S.L Lam, Shoaib M. & T.Srikanthan, "Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors", IEEE Third International Workshop on Electronic Design, Test and Applications (DELTA), pp. 237-242, K.L.Malaysia, Jan 2006. |
L.P.Yan, S.K.Lam , T.Srikanthan & J.G.Wu, "Energy Efficient Cache Tuning with Performance Bound", The Third IEEE International Workshop on Electronic Design, Test & Applications (DELTA'2006), pp.97-100, K.L.Malaysia, Jan 2006. |
Ravi Kumar Satzoda & C.H. Chang, "A Fast Kernel for Unifying GF(p) and GF(2^m) Montgomery Multiplications in a Scalable Pipelined Architecture", International Symposium on Circuits and Systems (ISCAS 2006), pp.3378-3381, Greece, Jan 2006. |
2005
Timothy Oliver and Douglas Maskell, “An FPGA Model for Developing Dynamic Circuit Computing”, IEEE Field-Programmable Technology, Singapore, December 2005. |
Siu-Yeung Cho, Jia Jun Wong, "Facial Recognition By Localised Gabor Features," 8th International Workshop on Advanced Image Technology, Korea, 2005. |
Willis, Gayathri Venkataraman, Sabu Emmanuel, Amitabha Das, "FPGA Implementation of Cluster Formation Algorithms in Mobile Ad-hoc Networks," Intelligent Sensors, Sensor Networks and Information Processing, ISSNIP05, pp. 19-24, Australia, December 2005. |
Yu Yu, Jussipekka Leiwo & Benjamin Premkumar, "Program Obfuscation via Oblivious Circuit Evaluation," SKLOIS Conference on Information Security and Cryptology, China, December 2005. |
A.Ray, J.G.Wu, T.Srikanthan, "Estimating Processor Performance of Standard Library Function," 2nd International Conference on Embedded Software and Systems (ICESS-05), China, December 2005. |
Y.Wang, Jussipekka Leiwo, T.Srikanthan, "A unified atchitecture for crypto-processing for embedded systems," 2nd International conference on Embedded Software and Systems (ICESS-05), pp. 37-42, China, December 2005. |
M.Sindhwani, T.Srikanthan, "Framework for Automated Application-Specific Optimization of Real-Time Operating Systems," Fifth International Conference on Information, Communications and Signal Processing (ICICS 2005), pp 1416 - 1420, Thailand, December 2005. |
| A.P.Vinod, E.M.K.Lai and D.L.Maskell, “High-Speed Low Complexity Wavelet Filter Banks For DNA Microarray Image Denoising”, 12th International Conference on Biomedical Engineering (ICBME 2005), 2005. |
Leiwo, J. and Maskell, D.L., “Strategies for cost efficient security evaluations”, TENCON 2005, Melbourne, Australia, November 2005. |
Lee Yi Shian, Timothy F. Oliver and Douglas L. Maskell, “Reconfigurable Computing: Peripheral Power and Area Optimization Techniques”, TENCON 2005, Melbourne, Australia, November 2005. |
Woods, G.S. and Maskell, D.L., “Improving Group Delay Measurement Accuracy using the FM Envelope Delay Technique”, TENCON 2005, Melbourne, Australia, November 2005. |
K.Vivekanandarajah, T.Srikanthan, C.T.Clarke, "Profile Directed Optimization of Instruction Cache hierarchy for Low Power Embedded Systems," IEEE CS Annual Symposium on VLSI (ISVLSI), October 2005. |
R.K.Satzoda, C.H.Chang, "VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers," Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC 05). Lecture Notes in Computer Science LNCS 3740, Springer-Verlag, pp. 693-706, Singapore, October 2005. |
Sai Ganesh Gopalan, Gayathri Venkataraman, Sabu Emmanuel, "FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-hoc Networks," Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), pp. 714-727, Singapore, October 2005. |
S.K.Lam, Deng Yun, T.Srikanthan, "Morphable Structures for Reconfigurable Instruction Set Processors," Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), Vol. 3740,pp. 450-463, Singapore, October 2005. |
J. Yanto, T.F. Oliver, B. Schmidt and D.L. Maskell, “Biological Sequence Analysis with Hidden Markov Models on an FPGA”, Asia-Pacific Computer Systems Architecture Conference, Singapore, October 2005. |
K.S. Tham and D.L. Maskell, “Software-oriented System-level Simulation for Design Space Exploration of Reconfigurable Architectures”, Lecture Notes in Computer Science, Springer-Verlag, Vol 3740, pp. 391-404, October 2005. |
J. Yanto, T.F. Oliver, B. Schmidt and D.L. Maskell, “Biological Sequence Analysis with Hidden Markov Models on an FPGA”, Lecture Notes in Computer Science, Springer-Verlag, Vol 3740, pp. 429-439, October 2005. |
J.G.Wu, T.Srikanthan, Chengbin Yan, "Minimizing Power in Hardware/Software Partitioning," Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), LNCS,vol.3740, pp.580-588, Singapore, October 2005. |
Gayathri Venkataraman, Sabu Emmanuel, T.Srikanthan, "DASCA: A Degree and Size based Clustering Approach for Wireless Sensor Networks," IEEE, International Symposium of Wireless Communication Systems (ISWCS 2005), pp. 508-512, Sienna, September 2005. |
L.Wang, C.G.Leedham, "A Thermal Hand Vein Pattern Verification System," 3rd International Conference on Advances in Pattern Recognition, UK, August 2005. |
A.P.Vinod and Irfan Setiawan, “A minimal-difference differential coefficients method for low complexity FIR filter realization,” Proceedings of the Eight IEEE International Symposium on Signal Processing and its Applications, vol. 1, pp. 155-158, Sydney, Australia, August 2005. |
A.Ray, T.Srikanthan, J.G.Wu, "Practical Techniques for Performance Estimation of Processors," 2005 International Workshop on System-on-Chip, Canada, July 2005.
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K.Baskaran, T.Srikanthan, "Hardware OPErating Systems (HOPES) for Run-time Reconfigurable Platform for Embedded devices," IEEE International Workshop on Computer Architecture for Machine Perception, Italy, July 2005. |
Timothy Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens and Douglas Maskell, “Muliptiple Sequence Alignment on an FPGA”, HiPCoMB 2005, Fukuoka, Japan, July, 2005. |
K.Baskaran, J.G.Wu, T.Srikanthan, "Application-Specific Partitioning Algorithm for Run-time Reconfigurable Platform for Embedded Devices," Engineering of Reconfigurable Systems and Algorithms, USA, June 2005. |
K.Vivekanandarajah & T.Srikanthan, “Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems”, IEEE International Workshop on Rapid System Prototyping, pp.151-157, Canada, June 2005. |
Timothy Oliver, Bertil Schmidt, Douglas Maskell and A.P. Vinod, “A Reconfigurable Architecture for Scanning Biosequence Databases”, ISCAS 2005, Kobe, Japan, pp. 4799-4802, May, 2005. |
A.P.Vinod and E.M.K.Lai, “Comparison of the Horizontal and the Vertical Common Subexpression Elimination Methods for Realizing Digital Filters,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 496-499, Kobe, Japan, May 2005. |
A.P.Vinod and E.M.K.Lai, “Design of Low Complexity High-speed Pulse-shaping IIR Filters for Mobile Communication Receivers,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 352-355, Kobe, Japan, May 2005.
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A.P.Vinod and E.M.K.Lai, “Optimizing Vertical Common Subexpression Elimination Using Coefficient Partitioning for Designing Low Complexity Software Radio Channelizers,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 6, pp. 5429-5432, Kobe, Japan, May 2005. |
C.H.Chang, Ravi Kumar Satzoda & Sekar Swaminathan, “ A Novel Multiplexer Based Truncated Array Multiplier” , IEEE International Symposium on Circuits and Systems (ISCAS), pp.85-88, Kobe, Japan, May 2005. |
Yu Yu, Jussipekka Leiwo, Benjamin Premkumar, "On the Possibility of Privacy-preserving Biometric Identification," LNCS Privacy Enhancing Technologies 2005, Dubrovnik, Croatia, May 2005. |
Y.He, C.H.Chang, H.A.H.Fahmy, "A novel covalent redundant binary Booth encoder," IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 69-72, Kobe, Japan, May 2005. |
Y.He, C.H.Chang, J.Gu, "An area efficient 64-bit square root carry-select adder for low power applications," IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 4082-4085, Kobe, Japan, May 2005. |
B.Cao, T.Srikanthan, C.H.Chang, "A new design method to modulo 2n1 squaring" IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 664-667, Kobe, Japan, May 2005. |
B.Cao, C.H.Chang, T.Srikanthan, "A new formulation of fast diminished-one multioperand modulo 2n1 adder," IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 656-659, Kobe, Japan, May 2005. |
Y.Shao, C.H.Chang, "Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition," IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 3833-3836, Kobe, Japan, May 2005. |
Y.Shao, C.H.Chang, "A versatile speech enhancement system based on perceptual wavelet denoising," IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 864-867, Kobe, Japan, May 2005. |
C.H.Chang, S.Menon, B.Cao, T.Srikanthan, "A Configurable Dual Moduli Multi-Operand Modulo Adder," IEEE Int. Symposium on Circuits and Systems (ISCAS-2005), pp. 1630-1633, Kobe, Japan, May 2005. |
F.Xu, C.H.Chang, C.C.Jong, "I2CRA: Contention resolution algorithm for intra- and inter-coefficient common subexpression elimination," IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), pp. 1823-1826, Kobe, Japan, May 2005. |
Wang Yi, Jussipekka Leiwo & T.Srikanthan, “ Efficient High Radix Modular Multiplication for High-speed Computing in Re-configurable Hardware” , IEEE International Symposium on Circuits and Systems, pp.1226-1229, Kobe, Japan, May 2005. |
S.Suchitra, S.Sneha, T.Srikanthan & C.T. Clarke, “ Elimination of Sign Precomputation in Flat CORDIC” , International Symposium on Circuits and Systems (ISCAS), pp.3319-3322, 2005. |
Ravi Kumar Satzoda, K.H.Quek & T.Srikanthan, “Analysis of Design Complexity of Datapaths”, Synopys Users Group Conference, Online proceedings, Singapore, June 2005. |
S.Bhattacharyya, T.Srikanthan, K.Vivekanandarajah, "Area and Power Efficient Pattern Prediction Architecture for Filter Cache Access Prediction in the Instruction Memory Hierarchy," IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT'05), pp. 345-348, Taiwan, April 2005. |
S.Udit, F.Xu, C.H.Chang, C.C.Jong, "sys-fir: A compiler for evaluating VLSI performance metrics of reduced adder cost FIR filters," IEEE Int. Symp. on Low-power and High-speed Chips, Cool Chips VIII, pp.339-346, Yokohama, Japan, April 2005. |
Yu Yu, Jussipekka Leiwo, Benjamin Premkumar, "Securely Utilizing External Computing Power," IEEE International Conference on Information Technology: Coding and Computing, USA, April 2005. |
Gayathri Venkataraman & Sabu Emmanuel, “Size and Hop Restricted Cluster Formation in Mobile Ad-hoc Network”, IASTED International Conference on Networks and Communication Systems (NCS 2005), Thailand, Apr 2005. |
Tim Oliver, Bertil Schmidt and Douglas Maskell, “Hyper Customized Processors for Bio-Sequence Database Scanning on FPGAs”, FPGA’05, Monterey, California, Feb. 2005. |
2004
Xiaoyun Deng, Pengfei Xu, and Chip-Hong Chang, “Self organizing topological tree for skin color detection,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004), Taiwan, pp. 1097-1100, December 6-9, 2004. |
F. Xu, J. Chen, C. H. Chang and C. C. Jong, “A modified reduced adder graph algorithm for multiplier block minimization in digital filters,” in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, pp. 705-708, December 6-9, 2004. |
C. H. Chang, Y. He and J. Gu, “An alternative scheme for redundant binary multiplier,” in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, pp. 33-36, December 6-9, 2004. |
J.G. Wu & T Srikanthan, “A Branch-and-Bound Algorithm for Hardware/Software Partitioning”, IEEE Symposium on Signal Processing and Information Technology (ISSPIT ), Rome, Italy, pp. 526-529, Dec. 2004. |
Z.Jin, M.Sindhwani, T.Srikanthan, "RTOS Acceleration on Soft-core Processors Using Instruction Set Customization," International Conference on Field Programmable Technology (FPT 2004), pp. 371-374, Australia, Dec 2004. |
Chua, C.Y., Lim, S. and Maskell, D.L., "High Performance, Reliable and Flexible Computing Payload for Space Missions", TENCON 2004, Chiang Mai, Thailand, Nov., 2004. |
| Oliver, T.F., Mohammed, S., Krishna, N.M. and Maskell, D.L., "Accelerating an Embedded RTOS in a SOPC Platform", TENCON 2004, Chiang Mai, Thailand, Nov., 2004. |
Maskell , D.L. and Woods, G.S., "Adaptive Subsample Delay Estimation using Windowed Correlation", TENCON 2004, Chiang Mai, Thailand, Nov., 2004. |
Maskell , D.L. and Woods, G.S., " A Hardware Efficient Subsample Adaptive Quadrature Delay Estimator for Sinusoidal Signals ", TENCON 2004, Chiang Mai, Thailand, Nov., 2004. |
S.Suchitra, S.K.Lam, T.Srikanthan, "Novel Schemes for High-Throughput Image Rotation," 38th Annual Asilomar Conference on Signals, Systems, and Computers, pp.1884-1888, Nov 2004. |
K.Baskaran, T.Srikanthan, "Issues And Approaches to Run-Time Reconfigurable Computing Platform for Embedded Systems," IADIS International Conference Applied Computing 2004, Portugal, 2004. |
S.K.Lam, T.Srikanthan, C.T.Clarke, Eugene Low H.S, "Achieving Hardware-Efficient Neural Network Based Pattern Recognition System Through Linear Approximation," Asilomar Conference on Signals, Systems, and Computers, pp. 451-455, Nov 2004. |
S.Suchitra, C.S.Lim, T.Srikanthan, "Array based Architecture for EZW Image Encoding on FPGA using Handel-C," 38th Annual Asilomar Conference on Signals, Systems, and Computers, pp.447-450, Nov 2004. |
M Sindhwani, Tim Oliver, Douglas L Maskell and T Srikanthan, “RTOS Acceleration Techniques - Review and Challenges”, Sixth Real-Time Linux Workshop, Singapore, pp.123-128, Nov 2004. |
B. Krishnamoorthy and T Srikanthan, "A Hardware Operating System based Approach for Run-time Reconfigurable Platform of Embedded Devices", Sixth Real-Time Linux Workshop, pp111-116 , November 3-5, 2004, Singapore. |
B. Krishnamoorthy, J.G Wu and T Srikanthan, "Hardware Partitioning Algorithm for Reconfigurable Operating System in Embedded Systems", Sixth Real-Time Linux Workshop, pp. no. 117-123 , November 3-5, 2004, Singapore. |
S.Suchitra, S.K.Lam, T.Srikanthan, "High-Throughput Image Rotation using Sign-Prediction based Redundant CORDIC Algorithm," IEEE International Conference on Image Processing, pp. 2833-2836, Singapore, October 2004. |
C.S. Lim, H. Tian and T.Srikanthan, "An Automated Technique for High Speed Segmentation of Endoscopic Images",International Symposium on Intelligent Multimedia, Video & Speech Processing, ISIMP2004, The Hong Kong Polytechnic University, Hong Kong, pp. 186-189, October 20-22, 2004. |
L. Li, W.A. Weliamto, H.S. Seah, ''Cluttered Scene Understanding and Augmentation,'' 4th IASTED International Conference on Visualization, Imaging, and Image Processing, 2004, pp. 664-669. |
W.A. Weliamto, L. Li, H.S. Seah, ''Enhancing the Stability of Harris-Plessey Corner Detection,''4th IASTED International Conference on Visualization, Imaging, and Image Processing, 2004, pp. 318-323. |
Luo Jianwen, Jong Ching Chuen, "Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs ," Euromicro Symposium on Digital System Design (DSD'04), pp. 244-248, France, September 2004. |
Woods, G.S., Maskell, D.L. and Kerans, A., "New angle-of-arrival measurement technique for over ocean propagation studies", ICCS 2004, 6-9 Sept., 2004, Singapore. |
P.K. Meher, T. Srikanthan, J.Gupta, and H.K. Agarwal: ‘Low-Complexity Unified-Adaptive Compression of Biomedical Images Using Integer Hartley Transform’, 1st International Bioengineering Conference 2004, pp.125 - 128, September 2004. |
Gayathri Venkataraman, Sabu Emmanuel, T.Srikanthan, "A Novel Distributed Cluster Maintenance Technique for High Mobility Ad-hoc Networks," IEEE, First International Symposium of Wireless Communication Systems (ISWCS 2004), pp125-129, Mauritius, September 2004. |
W.A.Weliamto, Li Li, H.S.Seah, "Robust Point Correspondence and Pose Estimation," 7th IASTED International Conference on Computer Graphics and Imaging, pp. 411-416, Hawaii, August 2004. |
Wu Jigang & T Srikanthan, “Finding High Performance Solution in Reconfigurable Mesh-connected VLSI Arrays”, Ninth Asia-Pacific Computer Systems Architecture Conference, Lecture Notes in Computer Science, Vol. 3189, pp. 440-448, Aug. 2004 |
K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya, “Dynamic Filter Cache for Low Power Instruction Memory Hierarchy ”, EUROMICRO Symposium on Digital System Design, IEEE CS Press, Rennes, France, pp. 607-610, August/September, 2004. |
Y.Chen, C.G.Leedham, "The Multistage Approach to Information Extraction in Degraded Document Images," 17th International Conference on Pattern Recognition, UK, August 2004. |
Gayathri Venkataraman, Sabu Emmanuel, T.Srikanthan, "A Size-limited Cluster Maintenance Technique for Mobile Ad-hoc Networks," Fourth International Symposium Communication Systems, Networks and Digital Signal Processing (CSNDSP'2004), pp. 310-313, Uk, July 2004. |
H.Tian, T.Srikanthan, C.S.Lim, "Iris Filter: The VLSI Perspective," Fourth International Symposium on Communication System, Networks, and Digital Signal Processing, (CSNDP-2004, UK), pp. 617-621, UK, July 2004. |
J.G.Wu, T.Srikanthan, "Local Optimal Algorithm for High Performance Solution of Re-configurable VLSI Arrays," 4th International Symposium on Communication Systems, Networks and Digital Signal Processing, pp.622-625, UK, July 2004. |
S.K. Lam, T. Srikanthan. and K.H. Leow, "Efficient Memory Structures for Dynamic Multicast Routing Architecture", 4th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP), July 2004, pp. 609-612. |
Y.Wang, Jussipekka Leiwo, T.Srikanthan, "Efficient High Radix Modular Multiplication for High-speed Computing in Re-configurable Hardware," International Proceedings on applied Cryptography and Network Security(ACNS'04), China, June 2004. |
| G. S. Woods , A.J. Kerans and D.L. Maskell, "Simulated Angle-of-Arrival Measurements for an Over Ocean Microwave Radio Link", URSI Commission F, Triennium Open Symposium , Cairns, Australia, 1-4 June 2004. |
| F. Xu, C. H. Chang and C. C. Jong, “A new contention resolution algorithm for the design of minimal logic depth multiplierless filters,” in Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004. |
J.G.Wu, T.Srikanthan, "Fast Rerouting Mesh-connected VLSI Arrays," IEEE International Symposium on Circuits and Systems, Vol. II, pp. 949-952, Canada, May 2004. |
A. Ray, J.G Wu and T. Srikanthan, “Knapsack Model and Algorithm for HW/SW Partitioning Problem”, International Conference on Computational Science (ICCS 2004), Vol. 1, pp.203-206, 2004. |
Maskell , D.L. and Woods, G.S. and Kerans, A., "A Hardware Efficient Implementation of an Adaptive Subsample Delay Estimator", ISCAS 2004, Vancouver, Canada, May, 2004. |
| F. Xu, C. H. Chang and C. C. Jong, “Efficient algorithm for common subexpression elimination in digital filter design,” in Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP-2004), Montreal, Canada, May 2004. |
| P. Xu and C. H. Chang, “Self-organizing topological tree,” in Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004. |
| C. H. Chang and P. Xu, “Frequency sensitive self-organzing maps and its application in color quantization,” in Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004. |
| F. Xu, C. H. Chang and C. C. Jong, “HWP: a new insight into canonical signed digit,” in Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004. |
| B. Cao, T. Srikanthan and C. H. Chang, “Design of residue-to-binary converter for a new 5-moduli superset residue number system,” in Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004 . |
| J. Gu, C. H. Chang and K. S. Yeo, “An area and energy efficient IP core for scalar product computation,” in Proc. Int. Symp. on Low-power and High-speed Chips, Cool Chips VII, Yokohama, Japan, April 2004. |
T. Oliver and B. Schmidt, "High Performance Biosequence Database Scanning on Reconfigurable Platforms", Third IEEE International Workshop on High Performance Computational Biology (HiCOMB), April 26, 2004. |
Woods, G.S., Kerans, A.J. and Maskell, D.L., "Measuring Angle-of-Arrival in Over Ocean Propagation Experiments", WARS 2004, Hobart, Australia, Feb., 2004. |
X. Deng, C. H. Chang and E. Brandle, "A new method for eye extraction from facial image," in Proc. 2 nd IEEE Int. Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 29-34, January 2004. |
Z. Ye and C. H. Chang, "Local search method for FIR filter coefficients synthesis," in Proc. 2 nd IEEE Int. Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 255-260, January 2004. |
Z. Ye, R. K. Satzoda, U. Sharma, N. Nazimudeen and C. H. Chang, "Performance evaluation of direct form FIR filter with merged arithmetic architecture," in Proc. 2 nd IEEE Int. Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 407-409, January 2004. |
K. Vivekanandarajah, T. Srikanthan, S. Bhattacharya, "Decode Filter Cache for Energy Efficient Instruction Cache Hierarchy in Super Scalar Architectures",in proceedings of the IEEE/ACM Asia South Pacific Design Automation Conference, (ASP-DAC'04), Yokohama, Japan, January 2004. |
2003
Maskell, D.L. and Woods, G.S., "An Adaptive Subsample Delay Estimator using a Quadrature Demodulator", ICICS-PCM 2003, Singapore, Dec., 2003. |
P.K. Meher, T. Srikanthan, J. Gupta, and H.K. Agarwal, "Controlled-Accuracy-Lossy Compression Using Integer Hartley Transform" , Proceedings of The IEEE International Symposium on Consumer Electronics (ISCE-2003), December 2003. (CD Rom) |
P.K. Meher, T. Srikanthan, J. Gupta, and H.K. Agarwal, "Near Lossless Image Compression Using Lossless Hartley Like Transform",Proceedings of The Fourth IEEE Pacific-Rim Conference On Multimedia, Singapore, December 2003. (CD Rom) |
P.K. Meher, T. Srikanthan and A.K. Rath, "Design Of An Efficient Embedded Merged DSP Microcontroller Using Configurable Cores",Proceedings of The IEEE International Symposium on Consumer Electronics (ISCE-2003), December 2003. (CD Rom) |
Khor, A.K., Leedham, C.G. and Maskell, D.L., "Collision and Impact Force Computation for Virtual Reality Applications", TENCON 2003, Bangalore, India, Vol 2, pp. 853-857, Oct., 2003. |
Maskell, D.L. and Woods, G.S., "Adaptive Subsample Delay Estimation using a Windowed Quadrature Phase Detector", TENCON 2003, Bangalore, India, Vol 1, pp. 91-94, Oct., 2003. |
C.H. Chang, M. Zhang and J. Gu, "A novel low power low voltage full adder cell", in Proc. 3th IEEE/EURASIP International Symposium on Image and Signal Processing and Analysis (ISPA-2003), Rome, Italy, pp.454-458, September 2003. |
B. Cao, C.H. Chang and T. Srikanthan, "Adder based residue to binary converters for a new balanced 4-moduli set", in Proc. 3th IEEE/EURASIP International Symposium on Image and Signal Processing and Analysis (ISPA-2003), Rome, Italy, pp.820-825, September 2003. |
Z. Ye and C.H. Chang, "A hybrid CSA tree for merged arithmetic architecture of FIR filter", in Proc. 3th IEEE/EURASIP International Symposium on Image and Signal Processing and Analysis (ISPA-2003), Rome, Italy, pp.449-453, September 2003. |
P.K. Meher and T. Srikanthan: 'A Scalable Multiplier-less Fully-Pipelined Architecture for VLSI Implementation of the Discrete Hartley Transform', The 2003 IEEE International Symposium on Signals, Circuits and Systems' (SCS-2003), Iasi, Romania, pp. 393-396, July 2003. |
C.G. Leedham, Y. Chen, K. Takru, J. Tan and M. Li, "Comparison of some thresholding algorithms for text/background segmentation in difficult document images",Proc. 7 th Int. Conf. on Document Analysis and Recognition, Scotland, Vol. 2, pp 859 -865, 2003. |
Timothy F. Oliver, Douglas L. Maskell: "Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications."Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, (ERSA) June 23 - 26, pp 141-146, 2003. |
K. Vivekanandarajah, T. Srikanthan, S. Bhattacharya, P.V. Kannan, "Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design", in Proc. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2003), Alberta, Canada, pp.44-47, June/July, 2003. |
K. Vivekanandarajah, T. Srikanthan, C. Clarke, S. Bhattacharya, "Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design" , in Proc Embedded Systems and Applications Conference 2003 (ESA'03), Las Vegas, Nevada, USA, pp.210-215, June 2003. |
P.K. Meher, T. Srikanthan, Mahesh Kumar, M. and Arunkumar, S. "Low-power transform-domain coding by separable two-dimensional Hartley-like transform", Proceedings 2003 International Workshop on Methodologies in Low-power Design, Monte Carlo Resort, Las Vegas, Nevada, USA, June 23 - 26, 2003. |
J.G. Wu & T. Srikanthan, Chandni R. Patel, "A Low Power Algorithm for Reconfigurable VLSI/WSI Arrays", in Proceedings of The 2003 International Workshop on Methodologies in Low Power Design ( MLPD'03 ), Las Vegas, USA. June 23-26, 2003. CD-ROM (ISBN: 1-892512-40-8), CSREA Press. |
J.G. Wu & T Srikanthan, "On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays", in Proceedings of The International Conference on Computational Science 2003 (ICCS 2003), Melbourne, Australia. Lecture Notes in Computer Science 2659, vol. 3, pp.360-366, Springer-Verlag Press, 2003. |
S.K. Lam, D.K. Chaudhary and T. Srikanthan, "Low Cost Logarithmic Techniques for High Precision Computations", IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, Vol. 5, pp. 125-128, May 2003. |
H. Tian, S.K. Lam. and T. Srikanthan, "Implementing Otsu's Thresholding Process Using Area-Time Efficient Logarithmic Approximation Unit", IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, Vol. 4, pp. 21-24,May 2003. |
K.H. Quek, S.K. Lam, N.K. Agrawal and T. Srikanthan, "Architectural Design and Analysis Toolbox to Implement Shortest Path Algorithms in Hardware", IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, Vol. 3, pp. 224-227, May 2003. |
J.G. Wu & T Srikanthan, "Partital Rerouting Algorithm for Reconfigurable VLSI Arrays", in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, May, 2003. Vol. 5, pp.641-644. IEEE Press. |
B. Cao, T. Srikanthan and C.H. Chang, "Design of a high speed reverse converter for a new 4-moduli set residue number system", in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, May, Vol. IV, pp. 520-523, May 2003. |
B. Cao, C.H. Chang and T. Srikanthan, "New efficient residue-to-binary converters for 4-moduli set {2 n-1, 2 n, 2 n+1, 2 n+1-1}", in Proc. IEEE Inernational Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. IV, pp. 536-539, May, 2003. |
M. Zhang, J. Gu and C. H. Chang, "A novel hybrid pass logic with static CMOS output drive full-adder cell" , in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. V, pp. 317-320, May, 2003. |
J. Gu and C.H. Chang, "Ultra low voltage, low power 4-2 compressor for high speed multiplications" , Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. V, pp. 321-324, May, 2003. |
M. Shibu, C. H. Chang and R. Xiao, "FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging" , Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. II, pp. 452-455, May, 2003. |
C.S. Lim, H. Tian, G. Sadana and T. Srikanthan, "High speed technique for automatic guidance of micro-robotics in endoscopic procedures",4th Annual IEEE EMBS Conference on Information Technology Applications in Biomedicine (ITAB), Birmingham, UK, pp. 130-134, April 2003. |
G. Singh, A. Panda, S. Bhattacharyya T. Srikanthan. "Vector Quantization Techniques for GMM Based Speaker Verification", IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, April, 2003. |
C.H. Chang, R. Xiao and T. Srikanthan, "An adaptive initialization technique for color quantization by self organizing feature map", IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, Vol. III, pp. 477-480, April, 2003. |
J. Gu and C.H. Chang, "Low voltage, low power (5:2) compressor cell for fast arithmetic circuits", IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, Vol. II, pp. 661-664, April, 2003. |
X. Yang and C.H. Chang, "A feasibility study of embedded Linux for the software defined radio", 2003 IEEE Sarnoff Symposium on Advances in Wired and Wireless Communications, New Jersey, USA, pp. 131-134, March 2003. |
X. Yang and C.H. Chang, "A practical approach for automatic recognition and identification of digital modulations", 2003 IEEE Sarnoff Symposium on Advances in Wired and Wireless Communications , New Jersey, USA, pp. 135-138, March 2003. |
J.G. Wu and T. Srikanthan, "A Run-time Reconfiguration Algorithm for Degradable VLSI Array" , 16 th International Conference on VLSI Design, New Delhi, India, pp. 567-572, January 2003. |
2002
Woods, G.S., Page, R.L. and Maskell, D.L., "Ground Height Detection Sensor for Control of Harvesting Equipment", Asia Pacific Microwave Conference, Kyoto, Japan, Dec., 2002. |
W. Yu and C. Charayaphan, "FPGA Implementation of Non-Iterative ICA for Detecting Motion in Image Sequences" , 7th International Conference on Control, Automation, Robotics and Vision (ICARCV 2002), pp.1332-1336, December, 2002. |
W. Yu and C. Charayaphan, "Non-Iterative ICA for Detecting Motion in Image Sequences", International Conference on Neural Information Processing 2002, Simulated Evolution and Learning 2002 & Fuzzy Systems and Knowledge Discovery 2002, #1279, November, 2002. |
Maskell, D.L. and Woods, G.S., ''Discrete-time quadrature time-of-arrival estimator for determining the subsample delay between narrowband ultrasound signals,'' IEEE Ultrasonics Symposium, Munich, pp 845-848, Oct., 2002. |
Chandni Patel, T. Srikanthan and Sangeetha Narayan, "A Rotation-invariant Embedded Pattern Recognition System", 2002 IEEE International Conference on Industrial Technology, Vol. 1, pp. 88-92, Oct, 2002. |
S.K. Lam, T. Srikanthan, Nitin Goyal and Neeraj Tyagi, "Incorporating Area-Time Flexibility to a Binary Signed-Digit Adder" ,IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2002), Vol.1, pp.485-489, October 2002. |
C.S. Lim, T. Srikanthan, K.V. Asari and S.K. Lam, "Fuzzy-ART based image compression for hardware implementation", IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2002) , Vol.2, pp.147-150, October 2002. |
C.H. Chang, R. Xiao and T. Srikanthan, "A MSB-biased self-organizing feature map for still colour image compression", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2002), Vol.2, pp.85-88, October 2002. |
C.H. Chang, Z. Ye and M. Zhang, "Fuzzy-ART based digital watermarking scheme" , IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2002), Vol.1,pp.423-426, October 2002. |
H. Tian, T. Srikanthan, C.H. Chang and S.K. Lam, "An Efficient Architecture for Adaptive Progressive Thresholding" , IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2002), Vol.1, pp.513-516, October 2002. |
S.K. Lam and T. Srikanthan, "Accelerating the K-Shortest Paths Computation in Multimodal Transportation Networks", IEEE 5 th International Conference on Intelligent Transport Systems, pp.491-495, September 2002. |
K.H. Quek and T. Srikanthan, "Towards Efficient Roadway Network Topology with Pre-processing", IEEE 5 th International Conference on Intelligent Transport Systems, pp. 511-516, September 2002. |
A. Panda, T. Srikanthan and S. Bhattacharyya, "Compute Efficient Training Method for Gaussian Mixture Model Based Speaker Verification" ,2 nd WSEAS International Conference on Speech Signal and Image Processing [WSEAS ICOSSIP], Koukounaries, Skiathos Island, Greece, 25 th –28 th September, 2002. |
A. Ehrensperger, C.H. Chang and J.G. Ma, "Fixed-point DSP implementation of mixed demodulator for digital FM radio receiver", IEEE Int. Symp. on Consumer Electronics (ISCE'02), Erfurt, Germany, September 2002. |
C.H. Chang, M. Zhang and Z. Ye, "A content-dependent robust and fragile watermarking scheme", the 2 nd IASTED Int. Conf. on Visualization, Imaging and Image Processing (VIIP-2002), Malaga, Spain, September 2002. |
R. Xiao, C.H. Chang and T. Srikanthan, "A New Localized Learning Scheme for Self-Organizing Feature Maps" , the 2 nd IASTED Int. Conf. on Visualization, Imaging and Image Processing (VIIP-2002), Malaga, Spain, September 2002. |
X. Yang and C.H. Chang, "Bluetooth Enabled Embedded Linux" , Linux Kongress, Cologne, Germany, pp.14-29, 4 th – 6 th September, 2002. |
J.G. Wu, H. Schroder & T. Srikanthan, "New architecture and algorithms for degradable VLSI/WSI arrays" , in Proc. of 8th International Computing and Combinatorics Conference, 2002, Singapore ( COCOON'O2), 15 th –17 th July, 2002. Lecture Notes in Computer Science, 2387 (2002), 181-190 .(Springer-Verlag). |
H. Tian, T. Srikanthan, K.V. Asari and C.S. Lim, "A Hardware Efficient Technique for Rapid Lumen Segmentation from Endoscopic Images", Proceedings of 3rd International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP'2002), UK, pp.260-263, 15 th –17 th July, 2002. |
A. Panda, S. Bhattacharyya and T. Srikanthan, "Global Background Model Approach for Embedded Speaker Verification Systems" , Proceedings of 3rd International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP-2002). Staffordshire UK, pp.383-386, 15 th-17 th July, 2002. |
S. Bhattacharyya, T. Srikanthan and P. Krishnamurthy, "Speaker Verification - A VLSI Perspective", Proceedings of 3rd International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP-2002), Staffordshire UK, pp.379-382, 15 th-17 th July, 2002. |
S. Bhattacharyya, T. Srikanthan, S.K. Lam and K.H. Quek, "SystemC for Architecture Exploration and Energy Centric Power Management " ,Synopsys User Group Conference (SNUG) Singapore, June 2002. |
C.S. Lim, T. Srikanthan and K.V. Asari, "Fuzzy-ART based image compression for hardware implementation", IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Bali, Indonesia, 28 th –31 st May, 2002. |
C.S. Lim, S.S. Abeysekera, T. Srikanthan and S.K. Amarasinghe, "Multiple sequence families with efficient hardware architecture for use in spread spectrum watermarking", IEEE International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, Vol. 1, pp.761-764, 26 th –29 th May, 2002. |
J. Gu, C. H. Chang and K. S. Yeo, "An interconnect optimized floorplanning of a scalar product macrocell,"the 35th IEEE Int. Symp. on Circuits and Systems (ISCAS'02), Scottsdale, Arizona, USA., Vol. I, pp. 465-468, May 2002. |
H. Tian, T. Srikanthan, S.K. Lam and K.V. Asari, "Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction", the 5 th IEEE Southwest Symposium on Image Analysis and Interpretation, IEEE Proc. on Computer Society Press, Santa Fe, New Mexico, pp.255-259, 7 th – 9 th April 2002. |
R. Xiao, C.H. Chang and T. Srikanthan, "On the initalization and training methods for Kohonen self-organizing feature maps in color image quantization", the 1 st IEEE International Workshop on Electronic Design, Test and Applications (DELTA-2002), Christchurch, New Zealand, pp.321-325, January 2002. |
2001
N. Sudha, T. Srikanthan and B. Mailachalam, "Implementing 3-D self organizing map-based color quantization process in FPGA", Proceedings of Ninth International Conference on Advanced Computing and Communications (ADCOM), pp. 223-230, Bhubaneswar, Dec. 2001. |
C.S. Lim, S.S. Abeysekera, T. Srikanthan and S.K. Amarasinghe, "Multiple sequence families sets for use in spread spectrum watermarking for multimedia", IEEE International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2001, Nashville, Tennessee, USA, 20 th –21 st November, 2001. |
N. Sudha, T. Srikanthan and B. Mailachalam, "A VLSI implementation of 3-D self organizing map for applications in color image processing", Proceedings of ICICS 2001, Singapore, Oct. 2001. |
H. Tian, T. Srikanthan and K.V. Asari, "A recursive Otsu-Iris filter technique for high-speed detection of lumen region from endoscopic images", IEEE Computer Society Proceedings30th International Workshop on Applied Imagery and Pattern Recognition, AIPR -2001, Washington DC, USA, pp. 182-186, 10 th –12 th October, 2001. |
S. Bhattacharyya, M. Sindhwani and T. Srikanthan, "Scalable Multi-user Extensions to A Stand-Alone Digital Answering Machine", 5 thIEEE Asia Pacific International Symposium on Consumer Electronics (ISCE 2001), Malaysia, pp. 148-150, October 2001. |
S.K. Lam and T. Srikanthan, "VLSI Based Environment Modelling System for Dynamic Path Planning", Third International Conference on Information, Communications and Signal Processing (ICICS 2001), October 2001. |
M. Sindhwani and T. Srikanthan, "High Performance and Robust On-Board Computing for the X-Sat Satellite", Third International Conference on Information, Communications & Signal Processing, (ICICS 2001), October 2001. |
M. Sindhwani and T. Srikanthan, "Fault Tolerant Strategies for Interconnecting Subsystems of the X-Sat Satellite", Third International Conference on Information, Communications & Signal Processing, (ICICS 2001), October 2001. |
H. Schroder, T. Srikanthan, J.G. WU and H. Tiggler, "Reconfigurable Architectures for High-performance Computing on-board Small Satellites",Third International Conference on Information, Communications & Signal Processing (ICICS 2001), October, 2001. |
D.J. Ho, C.H. Chang, H.Z. Peh and R. Meyyappan, "Architecture of a hardware module for GSM vocoder", the 9 th International Symposium on Integrated Circuits, Devices and Systems (ISIC-2001), Singapore, pp. 362-365, September 2001. |
S. Bhattacharyya and T. Srikanthan, "Using High-Level Language for Rapid Prototyping of FPGA Based Solution", The 9 th International Symposium on Integrated Circuits, Devices & Systems (ISIC-2001), Singapore, September 2001. |
S. Bhattacharyya, T. Srikanthan and T. Krishnamurthy P, "Ideal GMM Parameters & Posterior Log Likelihood for Speaker Verification", IEEE International Workshop on Neural Networks for Signal Processing, 2001(NNSP-2001), Boston, USA, pp. 471-480, September 2001. |
S. Bhattacharyya and T. Srikanthan, "K-means Clustering Algorithm – A Hardware Perspective", WSES International Conference on Speech Signal and Image Processing, 2001, Malta, pp.179-184, September 2001. |
K.H. Quek and T. Srikanthan, " Improving Hierarchical Route Computations for Roadway Networks" , 4 th International IEEE Conference on Intelligent Transportation Systems, pp.112-117, 2001. |
B. Schmidt , H. Schroder & T. Srikanthan, "A SIMD Solution to Biosequence Database Scanning", PARCO'2001, 2001. |
S.M. Lee, F.L. Leong, S.Y. Tan, C.H. Chang and Y. Lian, "Static timing analysis : a systematic approach to stamp modeling of complex blocks", Synopsys User Group Conference (SNUG 2001), Singapore, 1 st June 2001. |
H. Schroder, E. Eridisinghe and B. Schmidt, "Image processing algorithms designed for on-board computing", ICIS, Singapore 2001. |
2000
Ari Wahyudi, Omandi Amos & T. Srikanthan, "A multimedia-evaluation of the Infineon Tricore", International Symposium on Consumer Electronics, Hong Kong, pp. 128-136, December 2000. |
K. H. Quek and T. Srikanthan, "A Hierarchical Representation Of Roadway Networks" , 7th World Congress on Intelligent Transportation Systems, November, 2000. |
H. Tian, T. Srikanthan and K.V. Asari, "An automatic segmentation algorithm for object region and boundary extraction", Proceedings ofInternational Conference on Multimedia Processing and Systems, IIT, Madras, India, pp. 220-223, 13 th –15 th August, 2000. |
H. Tian, T. Srikanthan and K.V. Asari, "Iris filter based automatic boundary enhancement and detection algorithm for endoscopic images" , Proceedings ofSecond International Symposium on Communication Systems, Networks & Digital Signal Processing, Bournemouth, Poole, U.K., pp. 369-374, 18 th –20 th July, 2000. |
M. Sindhwani, T. Srikanthan and K.V. Asari, "VLSI Efficient Discrete-Time Cellular Neural network Processor", Second International Symposium on Communication Systems Networks & Digital Signal Processing, 18 th –20 th July, 2000. |
H. Tian, T. Srikanthan and K.V. Asari, "A new approach for object boundary extraction based on heuristic search", Proceedings of the International Conference on Imaging Science, Systems, and Technology, USA, pp. 693-699, 26 th –29 th June, 2000. |
B. Gisuthan, T. Srikanthan and K.V. Asari , "A High Speed Flat CORDIC Based Neuron with Multi-Level Activation Function for Robust Pattern Recognition", IEEE International Workshop on Computer Architectures for Machine Perception (CAMP 2000), Padova, Italy, pp.87-94, 11 th –13 th September,2000. |
B. Gisuthan and T. Srikanthan, "FLAT CORDIC : a unified architecture for high-speed generation of trigonometric and hyperbolic functions" , IEEE Proc. of the 43 rd Midwest Symposium on Circuits and Systems, Vol 3, pp.1414-1417, 2000. |
B. Mailachalam and T. Srikanthan, "A robust parallel architecture for adaptive color quantization", Proc. International Conference on Information Technology : Coding and Computing, pp 164-169, 2000. |
J. Mattew, D. Radhakrishnan and T. Srikanthan, "Fast residue-to-binary converter architectures" ,42 nd Midwest Symposium on Circuits and Systems, Vol 2, pp.1090-1093, 2000. |
Articles:
D. Nye, S. Bhattacharyya and T. Srikanthan, "Rapid Prototyping-Losung: System Modellierung mit Handel-C", Design & Verification Magazine, pages 55-58, June-July/2002 Issue. Adapted to German Language from original whitepaper in English. Germany. |
White Paper:
| S. Bhattacharyya and T. Srikanthan, "New Approach to Rapid Prototyping of Area-Time Efficient FPGA Solutions",Celoxica. UK, 2001. |
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