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Past Projects:
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Undergraduate Internship Programme
(Research project of up to six months duration)
Suggested Project Titles and Descriptions:
Title: Application Profiling for Power Sensitive Embedded System Design
Profiling is an instrumental process for understanding application characteristics and has been previously employed in various compiler optimization techniques. It is envisioned that efficient application profiling targeted towards realizing power-efficient processor customization, instruction-set customization, and hardware-software partitioning will pave the way for designing future embedded systems. This project aims to develop efficient application profiling techniques that can be integrated into a design methodology for power-sensitive embedded systems. The candidate will be required to first identify characteristics of a given application that would influence the power consumption of the run-time system. Next, suitable techniques to rapidly identify these characteristics must be devised in order to aid the optimization process in various stages of the design methodology.
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Title: Architecture Modeling of a Hybrid Re-configurable System to Facilitate Co-Design Exploration
Software models of hardware are often employed to accelerate architecture development. Hardware designers can execute programs on these models to validate the performance and correctness of a proposed hardware design. In addition, software programmers can use these software models to develop and test software before the real hardware becomes available. This fast mechanism for design and test provides shorter time to market and much higher quality first silicon. This project aims to develop a simulation environment that is well suited for efficient co-design targeted for hybrid re-configurable system, which integrates processor core and re-configurable units on a system-on-chip. The design of such a hybrid re-configurable system entails a multitude of design parameters and necessitates a methodical design approach, which relies on a simulation environment. The efficacy of the simulation environment can then be evaluated by simulating the results of various existing co-design techniques in the proposed environment.
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Title: A Hardware Multicast Routing Engine for Computing Minimum Hop Shortest Paths
With the emergence of new generation applications that require multipoint (or group) communication such as multimedia conferences, shared workspace, distributed games and distributed simulation, there became a pressing need for multipoint communication protocols. One of the most challenging issues researched in multipoint communication is multicast routing. A standard approach used to determine the cheapest path available that meets the desired level of service is by computing the minimum hop shortest path. This project aims to develop a hardware accelerator for dynamic multicast routing in high-speed communication networks to facilitate on-demand computation of minimum hop shortest paths. The proposed technique should be verified and analyzed on software, before porting to the hardware platform. Comparison with conventional techniques must be performed to analyze the effectiveness of the proposed method.
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Title: VLSI Based Environment Modeling Strategy For Navigation Systems
Navigation systems such as mobile robots and Automated Guided Vehicles (AGV) play a significant role in intelligent transportation and route guidance applications of today. The challenges in these navigation systems include the problem of modeling the environment where the obstacles change dynamically. It is envisioned that a hardware unit for constructing the visibility graph of an environment becomes an efficient solution for the modeling process. This project aims to implement a visibility graph generation unit, which is capable of providing a reliable map of a dynamic environment in real-time for subsequent path-planning computations. The student is required to develop novel techniques based on logarithmic approximation methods with a binary search scheme for visibility graph generation, in an environment where the obstacles can be represented as convex and concave polygons. Performance measure and the hardware complexity can be studied through various implementation strategies that exploit the parallelism of the architecture. The architecture can be realized using hardware description language (i.e. VHDL) and verified through state-of-the-art simulation tools.
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Title: A Unified Binary Signed-Digit Number System Based Floating-Point Unit
Although the high-density integrated circuit technology of today have given rise to the realization of complex and sophisticated arithmetic processors, there remain a pressing need for efficient arithmetic algorithms to suit the power-delay-area demands of many applications. In addition, precision demanding applications require floating-point operations, which further frustrates the algorithmic development process. Recently, there has been an increased interest in the area of non-conventional implementations such as the redundant number systems based arithmetic units. The Binary Signed-Digit (BSD) number representation system is one such system, which offers the property of limited carry addition for radix-2 implementations. The aim of this project is to develop computer arithmetic algorithms for a high-speed BSD number system based floating-point unit. It is envisioned that the proposed architecture will exhibit a significant performance speed-up over existing implementations using the conventional floating-point operations.
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Title: Power-Efficient Single/Double Precision Binary Logarithmic Conversion Unit
Complex arithmetic operations such as division, multiplication, and computation of powers are often found in applications such as computer graphics and digital signal processing. These applications demand high-speed algorithms and binary logarithms are often used as an alternative to the complex operations due to its speed and simplicity. Previously, a low-cost linear approximation method for fixed-point binary logarithmic conversion has been developed, by employing a small minimal look-up table and computation unit. This project aims to extend the proposed method by developing power-efficient techniques for binary logarithmic conversion in the IEEE single/double precision for binary floating-point numbers. The resulting architecture can be realized using hardware description language (i.e. VHDL), and verified through state-of-the-art simulation tools.
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Title: Voice Authentication and Reconfigurable Systems
Voice Authentication is a task of compute-intensive steps. These steps involve high-resolution probability values and complicated arithmetic calculations, such as logarithms, exponentiation, and floating point division. To exemplify the need for alternative approaches it is interesting to learn that the operation of authenticating a person takes about 40 seconds on a high performance Desktop running Borland C++ or Matlab. This observation justifies the thrust towards dedicated hardware architecture to perform the job in less time and at low-cost. The subsequent research led to the formulation of novel techniques that can be ported to an FPGA or an ASIC, paving the way for a fast portable single-chip solution, which performs the job in the order of a few milliseconds. Students involved in this project will be exposed to speech recognition methods, the implementation of independent modules of a GMM based speech recognition system on a re-configurable architecture using modern rapid prototyping tools.
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Title: A hierarchical map extraction system
Geographical Information System (GIS) uses databases to maintain necessary information to identify specific points on a map. To find the optimum path in a large network incurs considerable amount of time and powerful processing platforms are sought for if the application demands real-time performance. Although hierarchical based routing is an attractive alternative, the accuracy of the hierarchical routing heavily depends on the appropriate partitioning of the roadway network to form the hierarchical database. Currently, a common GUI is being developed in Visual C++ to visualise the different maps (Singapore, UK, US-California) using the hierarchical representation. In this project, techniques for the automatic representation of a roadway network into a hierarchical representation, will be developed based on some predefined rule set. It is envisaged that heuristic optimisation algorithms will be applied to this hierarchical representation in order to compute near optimal paths at high speed. |
Title: Power Management Extensions to the Infineon Tricore Port of the C/OS-II RTOS
C/OS-II (http://www.ucos-ii.com) is a highly portable, ROMable, scalable, preemptive multitasking, real-time operating system (RTOS) kernel for microprocessors and micro-controllers. It is a thin RTOS that has been ported to many processors, including the Infineon Tricore TC10GP Unified Processor ( http://www.infineon.com/tricore). As the RTOS has a low memory footprint, it has been used for various embedded applications.
For most portable embedded systems, power consumption is a concern. Lower power consumption translates into longer battery life and fewer problems with heat dissipation. With this view, the TriCore offers a host of features for power management. There are four power-management modes: Run, Idle, Sleep and Deep Sleep. Techniques such as clock gating and clock frequency manipulation allow the designers to cater to extremely demanding power consumption requirements. Most of these features are available to software designers and can be configured on the fly. Even though a wealth of features are available to the software engineer, most features require to be performed in a particular order, taking into consideration the current system state. This naturally suggests that these features be presented to the system programmers through a uniform Application Programmer's Interface (API). It is suggested that these features be implemented as extensions to the RTOS.
The project aims to exploit the on-chip power management system of the Infineon TriCore to add power management features to the Infineon TriCore port of the C/OS-II RTOS. This would allow system designers using C/OS-II to incorporate power management into their applications at minimal cost.
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Title: The design of reconfigurable computing architectures for space applications
This project will look at the use of reconfigurable hardware, in particular, FPGAs for providing fault tolerant on-board computing facilities for space applications. The project will examine techniques whereby SRAM-based FPGAs which are dynamically reconfigureable are able to recover from radiation-incluced faults. This is likely to include a combination of fault tolerant design and the application of fault detection followed by dynamic reconfiguration of the faulty module. The detection and reconfiguration algorithm must be able target both logic faults and interconnect faults. This project will include both a theoretical appraisal and hardware (FPGA) development.
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Title: High-Speed Parallel Architectures for Speaker Modeling
Speaker modeling for voice authentication is a computationally complex problem that takes several minutes to execute even on powerful high-end processors. However, such a large execution time may not be acceptable in many applications where fast modeling of the speaker’s voice is required. This project aims to develop dedicated hardware architectures that exploit the parallelism inherent in the algorithms used in speaker modeling. In the proposed implementation, the preparation of the speaker model is done in two phases. First, the iterative K-Means clustering algorithm is run on the feature vectors to produce an initial model. Subsequently, the Bayesian Adaptation algorithm is applied to the initial model to compute the final speaker model. The various stages in the project would be a study of the algorithms, modeling the architecture in VHDL, simulation, logic synthesis and place-and-route using EDA tools, and prototyping on an FPGA development board. The performance of the resulting design would be benchmarked against the PC-based software implementation. |
For application forms, please click internship application here & TEP application here . |
