Title: High-Speed Parallel Architectures for Speaker Modeling

Speaker modeling for voice authentication is a computationally complex problem that takes several minutes to execute even on powerful high-end processors. However, such a large execution time may not be acceptable in many applications where fast modeling of the speaker’s voice is required. This project aims to develop dedicated hardware architectures that exploit the parallelism inherent in the algorithms used in speaker modeling. In the proposed implementation, the preparation of the speaker model is done in two phases. First, the iterative K-Means clustering algorithm is run on the feature vectors to produce an initial model. Subsequently, the Bayesian Adaptation algorithm is applied to the initial model to compute the final speaker model. The various stages in the project would be a study of the algorithms, modeling the architecture in VHDL, simulation, logic synthesis and place-and-route using EDA tools, and prototyping on an FPGA development board. The performance of the resulting design would be benchmarked against the PC-based software implementation.

Title: Time-Dependant Routing in Dynamic Transportation Networks

In a dynamic transportation network, the travel cost (such as travel time) associated with each link typically varies with time. In an ideal environment where the future travel costs could be predicted with reasonable accuracy, performing route computation on the basis of travel costs prevailing at the time of computation may not yield the best results. Instead, for each link, the travel cost that is likely to exist at a later time when the vehicle reaches that link as part of a planned route should be considered. This is known as the time-dependent shortest path problem. This project would involve a study and evaluation of the various approaches for computing the time-dependent shortest paths. The transportation network of a city along with a large volume of real traffic data would be used as the testbed for the experiments. A major goal of the project would be to empirically quantify the benefits in terms of travel-time savings of employing time-dependent routing based on accurate prediction of near-future traffic conditions in the place of static route computation.

Title: Mapping Area-Time Efficient Data-paths onto FPGAs

Area-time efficient realization of data-paths is desirable for maximizing the utilization of FPGAs (Field-Programmable Gate Arrays). Area-time optimizations can be performed at various level of design abstractions, e.g. during high-level or gate level synthesis. Since the designs at the higher level of abstractions is less confined to the physical architecture, optimizations at these levels usually lead to high quality results. This project aims to propose a strategy for mapping area-time efficient data-paths onto the reconfigurable space by taking into account the inherent architecture constraints of the FPGA. The scalability of the proposed method must be demonstrated by mapping data-paths from C functions with varying degree of complexity onto the FPGA architecture. In order to evaluate the effectiveness of the proposed technique, area-time results of the proposed technique must be compared with results of existing high-level optimization approaches.

Title: Run-Time Reconfiguration Strategies for Instruction Set Customization

The need for customization and flexibility has led to the popularity of reconfigurable architectures such as the FPGA (Field-Programmable Gate Array). Run-time reconfiguration can further increase the cost efficiency of these architectures by means of hardware virtualization. Commercial FPGAs facilitate partial reconfiguration, which allows for run-time reconfiguration of a hardware region without affecting the execution of the remaining section. However, the lack of tools and architecture support discourages the adoption of run-time reconfiguration in realistic applications. In addition, the minimal reconfiguration time of commercial FPGAs is still in the order of milliseconds, which is unacceptable for most applications. It is envisioned that the run-time reconfigurable capability of commercial FPGAs can be enhanced through a framework that enables self-reconfiguration. The goal of this project is to develop an efficient framework for self-reconfiguration in commercial FPGAs. The proposed framework should incorporate lightweight modules that are embedded within the reconfigurable architecture to enable partial reconfiguration. The benefits of the proposed framework can be demonstrated through simulations using realistic examples.

Title: Safety subsystem for Infineon TriCore/T-Kernel

The power train is the system that generates the force needed to propel the vehicle and transmits this force to its proper destination.  Power train control includes engine and transmission control.  The flexibility of microprocessor-based power train control systems allows the designer to deal effectively with the relatively large number of system elements.  However, this same flexibility requires a system to ensure that major constraints are continually satisfied while still enforcing safety requirements. The TriCore family of microcontrollers from Infineon includes a number of architectural and on-chip features that provide good support for the implementation of safety and reliability features in a system.  The efficient us of these features requires that they presented to the system or application layer using a consistent API.  The T-Engine software stack does not directly have any specific features that support (or prevent) the implementation of safety features.  This project aims to develop such a subsystem for a system running the T-Engine software stack on the Infineon TriCore CPU.